Select and apply a range of design methodologies for the design and deployment of FPGAs and SoPCs in modern digital systems and recognising the limitations of the techniques employed

1. Module code & title

ELE3004M- Programmable Logic Design

2.  Assessed

learning outcomes

• [LO1] Select and apply a range of design methodologies for the design and deployment of FPGAs and SoPCs in modern digital systems and recognising the limitations of the techniques employed 
• [LO2] Evaluate the range of technologies involved in the microelectronics sector and understand how changes can impact on design methodologies and demonstrate principles of secure data storage and analysis.
• [LO3] Evaluate design and analytical tools and techniques for the construction of FPGAs-based solutions.
• [LO4] Demonstrate an in-depth understanding of current industrial practice and communicate through high quality technical publications on complex engineering matters.
• [LO5] Plan and record self-learning and development as the foundation for lifelong learning/CPD.

3. Assessment title

Assessment < Series of Laboratory experiments in FPGA design >

4. Contribution to final module mark (%)

70%

5. Description of assessment task

This is Assessment < Series of Laboratory experiments in FPGA design

>and is an <individual> assignment.

This assessment requires response to a series of questions and activities related to a series of laboratory experiments in FPGA design.

•The activities listed in this assessment build in complexity to demonstrate the learner’s abilities in a range of skills and understanding of a range of topics.

•Any direct entry Level 3 students will need to put in time and effort to learn Verilog and Vivado and become proficient before they can attempt the assignments.

•To prepare for this assessment, students will be given weekly (ungraded) assignments that they need to complete.

•The final (graded) coursework will be a subset of questions similar to the ones that have already been provided in earlier in the ungraded weekly assignments.

Additional Information for Completion of Assessment:

You are strongly advised to complete all the tasks required in the Laboratory Handout and capture the relevant data during the practical session.

You may wish to use an Engineer’s Log Book or an electronic word document to record notes and salient results.

A good plan of completing the assignment is important and progress with the report writing throughout the academic year is essential. You should use and revisit the written report throughout the module delivery to improve its content. You are free to choose the technical report template but make sure the report is well written, clear, concise, and reflects the work carried out in the Lab. Further guidance will be provided during each Laboratory session.

Please ensure that for each question you provide the following in your submission:

• All solution steps and logic diagrams (to show what you are implementing)
• Provide all Verilog codes with good remark statements and proper variables (for inputs and outputs).
• Provide a block diagram of your design and also download the behavioral block diagram (extracted from Vivado)
• Write a testbench for each design to verify the simulation results. Include the test bench in the report corresponding to your simulated outputs.
• Synthesize the design on FPGA (where asked). Please carefully read the question and instructions provided on the coursework sheet to understand what is expected.
• Write a paragraph in the end to discuss your results (even if you could not get it to work)

6. Assessment submission instructions

This submission is: Individual work (delete as appropriate)

All work should be submitted by the deadline stated. Any late submissions will be subject to a lateness penalty in line with the University policy.

In cases of technical issues please email your assessment to: sepssubmissions@lincoln.ac.uk by the above deadline. Please include the module code and coursework title in the email subject.

Please note that links will NOT be accepted under any circumstances.

7. Date for return of mark and feedback

Please see the Hand In Dates.xls spreadsheet.

Note: all marks awarded are provisional until confirmed by the Board of Examiners.

8. Feedback format

A feedback rubric will be uploaded to Blackboard GradeCentre 15 working days following the coursework submission. Marks will be available in Gradecentre at this time

9. Use of Artificial Intelligence (AI) in this assessment

See box 11.

10. Marking criteria for assessment

See guidance notes for further information

40% of the marks will be awarded for problem solving and design.

40% of the marks will be awarded for writing a program and testbench relevant to the design and correctly simulating the design.

20% of the marks will be awarded for getting the design working and synthesizing it on an FPGA board

Please note that all work is assessed according to the University of Lincoln Management of Assessment Policy and that marks awarded are provisional on Examination Board decisions which take place at the end of the Academic Year.

11. Important Information on Dishonesty, Plagiarism and AI Tools

University of Lincoln Regulations define plagiarism as `the passing off of another person`s thoughts, ideas, writings or images as one`s own…’. Examples of plagiarism include the unacknowledged use of another person`s material whether in original or summary form. Plagiarism also includes the copying of another student`s work`. Plagiarism is a serious offence and is treated by the University as a form of academic dishonesty. For more information on examples of Academic Offences, please see the Academic Offence Guidance.

The use of AI tools: Not Permitted (delete as appropriate)

Please note, if you use AI tools in the production of assessment work where it is not permitted, then it will be classed as an academic offence and treated by the University as a form of academic dishonesty.

Students are directed to the University Regulations for details of the procedures and penalties involved.

For further information, see www.plagiarism.org